Photonics Systems for High Performance – CPO, Towards Photonics Chiplets Slides

Abstract: A major hurdle in developing next-generation systems for high-performance applications and industries that require handling large, secure data - such as System-in-Package (SiP) and System-on-Chip (SoC) - is the absence of low-latency, high-bandwidth, and high-density off-chip/chiplet/core interconnects. Achieving high-bandwidth chip-to-chip (or chiplet-to-chiplet) communication using electrical interconnects faces challenges like high substrate dielectric losses, reflections, impedance discontinuities, and susceptibility to crosstalk. This underscores the motivation to adopt photonics to address these challenges and enable low-latency, high-bandwidth communication. The objective is to develop a CMOS-compatible technology to support the next-generation photonic layer within 3D SiP/SoC, moving towards converged microsystems.