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ECTC 2020 Best Session Paper

Shu-Rong Chun, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chuei-Tang Wang, Jeng-Shien Hsieh, Tsung-Shu Lin, Terry Ku, Douglas Yu

  • EPS
    Members: Free
    IEEE Members: $11.00
    Non-members: $15.00
    Pages/Slides: 6
01 Jun 2020

A novel wafer-scale system integration solution, InFO_SoW (System-on-Wafer), has been successfully developed to integrate known-good chips arrays with power and thermal module for high performance computing. InFO_SoW eliminates the use of substrate and PCB by serving as the carrier itself. Close packed multiple chips arrays within a compact system enable the solution to reap the wafer-scale benefits such as low latency chip-to-chip communication, high bandwidth density and low PDN impedance for greater computing performance and power efficiency. In addition to heterogeneous chips integration, its wafer-field processing capability has enabled chiplet-based design for greater cost saving and design flexibility.This paper demonstrated the industry's first wafer-scale system integration package with InFO technology. Electrical characterization results revealed good process uniformity across the super large package of InFO_SoW. It is simulated to have about 15 % power saving of the interconnects with length of 30 mm due to lower surface roughness of InFO RDL. Thermal management of such high power in a compact system has been validated through scalable proof-of-concept (POC) thermal solution. The POC thermal solution proved its capability of dissipating 7000 W out of the 2-by-5 array dummy heater, whereby the maximal temperature of the dummy heater is kept below 90°C. In addition, InFO_SoW structural robustness has been verified through both InFO wafer-level quick torture and system-level reliability tests. Despite its super large package size, thermomechanical Chip-Package-Interaction (CPI) simulation study revealed that InFO_SoW has relatively low risk when compared to qualified Flip-Chip package with advanced Si-node.

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